Cyclone V - Counter not counting correctly

Hi,

I'm using just this one clock in my whole design because I do not feel ready (from the timequest point of view) to handle different clock domains. I've gone through this pain in a couple of previous designs and try to avoid this as far as possible in this design.

The clock that this counter is synchronized to is also the clock that I use for signal tap.

The only signals that come from outside the FPGA are the MISO and N_DREADY signals from the ADC. The N_DREADY signal is (as you can see in the signal tap attachment) the trigger to leave my "state 0" and to got to "state 1" which quiet often is not working well . . . .

These signal are set to "false path" in my sdc.

Do you think, that the cause for this can be found here? Should I observe this N_DREADY signal outside my state machine with a, say, edge detector and feed that information into the main SPI state machine with my errornous counter?

Regards,

Maik