Honored Contributor
Honored ContributorReply with embedded quotes is bad on this site!..
--- Quote Start --- --- Quote Start --- I recommend declare variable May be bringing out of "case" all works with "state_register" and make there only bool sign "need_be_inc_state_register". --- Quote End --- Sorry, I don't fully understand what you mean by this. --- Quote End --- I recommend declare variable "need_be_inc_state_register", set it always instead "state_register <= state_register + 1", and make "if (need_be_inc_state_register) state_register <= state_register + 1;" only once below all code -- carry out brackets. Although Quertus optimizer may make the same. And need be use this with "state_register_plus_1". --- Quote Start --- Do you mean, that even if my design is checked by timequest (and modelsim) that there is still the chance that the design fails... --- Quote End --- I is programmer and know 2 rules: 1. Each program contain at the least 1 error. 2. If count of errors ==0, go to 1. :) All may be... With 75 MHz instead 100 in FPGA these errors continues ? --- Quote Start --- --- Quote Start --- Or choice with "traditional" writing "state_register + 1" or x"61" in "when 0 =>" to drive mad LUTs... --- Quote End --- Sorry, I have also problems to understand this. --- Quote End --- All your problems with transition from 0 not to 1, and to 33, 64 and 65 ? I see to "when 0 =>" and pull out version: may be conflict with summator working and constant setting. --- Quote Start --- I'm pretty happy that somebody answered this. I already feared that this was so unusual that nobody would reply. --- Quote End --- Unreplied questions -- often event, also dread is bad state, even if jump need in situ ! (Sorry my Lingvo 5.0 if translation from rus-deutch is bad :) In your company absent more FPGA-developers ? I cardinal would be divide 100 states to 8 groups with 8 separate state counters and in exactly unproblem way use 9+ assigments of each. And may else problem with inputs in 3rd state -- new FPGA interprete its different as older. If in "if" they used... ...And will be set FPGA clock to 25 MHz, SignalTap to 200, cath 8 samples in "tact", if present tremor in inputs to versatile variants... May closely analyse conditions for "official" transition to 33, 64 and 65, try to change it...
