Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- This post for other forum -- read first glued message, here is discussed HPS-FPGA relations! --- Quote End --- Yeah, sorry, I really was not sure where to put this. --- Quote Start --- May recommend you to rewrite code with "equal" changes -- often this helps to avoid "strange" FPGA behavior through "dancing with tambourine" :) For example, change all "state_register <= state_register + 1" to direct "state_register <= 1", "state_register <= 2", ... etc., if exampled in "when 0 =>" with x"61". May be excluded summator and all will cured. --- Quote End --- This was my very first implementation of this. I had declared the state_register as integer and did always "state_register <= 1;", "state_register <= 2;", etc. With this I had the same problems. I tried to change to use the summator in order to fix it, but it gave the same results, so I started this thread in the forum. --- Quote Start --- Or declare variable "state_register_plus_1", each tact compute it as "state_register_plus_1 <= state_register + 1" and make "state_register <= state_register_plus_1" in appropriate places... --- Quote End --- I will try this . . . Thanks for the suggestion! --- Quote Start --- May be bringing out of "case" all works with "state_register" and make there only bool sign "need_be_inc_state_register". --- Quote End --- Sorry, I don't fully understand what you mean by this. --- Quote Start --- 100 competetive writies to register is very complex problem for multiplexor, may be split these state machine to 2, 3... --- Quote End --- Do you mean, that even if my design is checked by timequest (and modelsim) that there is still the chance that the design fails, just because I want to count to 100....? That seems really weird to me, but it explains, why I have this problem, right now. Can I implement something similar that is not synthesized with multiplexers? Is there some source of information on this topic regarding synthesis/FPGA design? I'm really interested in designing a rock solid system and was not aware, that counting to 100 can be that problem for the FPGA . . . . --- Quote Start --- Or choice with "traditional" writing "state_register + 1" or x"61" in "when 0 =>" to drive mad LUTs... --- Quote End --- Sorry, I have also problems to understand this. Thanks for your answer. I'm pretty happy that somebody answered this. I already feared that this was so unusual that nobody would reply. Maik