Honored Contributor
Honored ContributorThis post for other forum -- read first glued message, here is discussed HPS-FPGA relations!
May recommend you to rewrite code with "equal" changes -- often this helps to avoid "strange" FPGA behavior through "dancing with tambourine" :) For example, change all "state_register <= state_register + 1" to direct "state_register <= 1", "state_register <= 2", ... etc., if exampled in "when 0 =>" with x"61". May be excluded summator and all will cured. Or declare variable "state_register_plus_1", each tact compute it as "state_register_plus_1 <= state_register + 1" and make "state_register <= state_register_plus_1" in appropriate places... May be bringing out of "case" all works with "state_register" and make there only bool sign "need_be_inc_state_register". 100 competetive writies to register is very complex problem for multiplexor, may be split these state machine to 2, 3... Or choice with "traditional" writing "state_register + 1" or x"61" in "when 0 =>" to drive mad LUTs... ...Please, don`t work with text tabs and not upload examples with its ! It is enough 2 spaces to show a visible ident !
