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I'm not a VHDL expert
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It's not a VHDL problem. It's about imagining how the FPGA hardware works.
The reset case will be needed, if you have a different reset source than POR, e.g. a reset input that's resetting all or some registers without reloading the configuration. If you don't have it, you don't need the reset case.
Another option is to have an internal reset generator in your design, that is controlling the global reset signal. The the reset case would be needed, too. It's meaningful, if you require the POR reset to be released synchronously but don't have a hardware reset input.
Generally, it's no harm to include the reset case and a global reset signal with your design and wire it to a constant in the top entity. Then you're prepared for later extensions.
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