Cyclone reset/POR

CONF_DONE can't be read in user code. And you don't need to.

You can refer to the POR by setting initial values for signals. In Verilog, they are set from an initial block. You can also rely on the fact, that all Verilog registers respectively VHDL signals are initialized to zero unless you set the global "power-up don't care" synthesis option. So for synthesis, you would only need to specify non-zero initial content of registers. In ModelSim functional simulation howver, all registers have an unknown 'U' state. If the design is intended for simulation, you should also explicitely include the zero initialization.