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Altera_Forum
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11 years ago

Cyclone lll LVDS IO

Hi, Currently, we are using Cyclone lll FPGA for our application. We plan to interface LVDS output signals with sensor chip. We had assigned LVDS related O/P signal in bank 7 and bank 8(top ban...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

No, each output was driving a single receiver in a quad lvds receiver with internal termination. Because the receiver was terminated internally I couldn't remove the 100 ohm resistor so one channel in the receiver chip was dissipating 100mW all by itself.

I was just commenting about the fact that I got away without using the external 3R termination in our prototypes but I would never ship product that way. We re-layed out the board to move that one channel from the bottom to the side. Everything was cooler after that.