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Altera_Forum
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11 years ago

Cyclone lll LVDS IO

Hi, Currently, we are using Cyclone lll FPGA for our application. We plan to interface LVDS output signals with sensor chip. We had assigned LVDS related O/P signal in bank 7 and bank 8(top ban...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Hi Kevin,

Are you using 4 LVDS tx output to drive 1LVDS rx simultaneously? You are doing this to boost the current in the transmission line?

Won't that be sort of unstable? The standard LVDS was suppose to be differential signal with Vcm ~1.25V and Vod ~100-400mV