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Altera_Forum
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11 years ago

Cyclone lll LVDS IO

Hi, Currently, we are using Cyclone lll FPGA for our application. We plan to interface LVDS output signals with sensor chip. We had assigned LVDS related O/P signal in bank 7 and bank 8(top ban...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

To ensure the emulated LVDS output can perform as per the specifications, it is recommended to follow the required 3R resistor network. If without the network, then you could try to perform IBIS model simulation to check if the signal can meet the receiver input specification to ensure the interface can work.