Cyclone IVE, DDR2 memory x32 interface - VREF in banks with output only

Cyclone IV E, UBGA256 body, DDR2 memory x32 interface.

Bidirectional pins DQ, DQM, DQS - located in banks 3,4,6,7.

In banks 2 and 5 located part of addresses and control signals - output only.

All pins - SSTL Class 1;

All banks VCCIO=1.8V

In banks 3,4,6,7 with bidirectionsl DQ, DQS banks VREF pins connected to voltage VREF_DDR2 = VCCIO/2. It's clear for me.

Sould I also connect VREF pins of banks 2,5 - with SSTL Class 1 outputs only - to VREF_DDR2 - or better left VREF pins of banks 2,5 unconnected?

After reading "JEDEC STANDARD Stub Series Terminated logic for 1.8V (SSTL_18)", JESD8-15A.pdf

my opinion is - left VREF pins of banks 2,5 unconnected.

I'm interesting your experience.