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I suggest you'll have to use an independent, fixed clock to measure the frequency of your changeable clock. This will allow you to determine whether the clock is above of below a threshold - say 10MHz. I suggest you keep the threshold well away from 5MHz. You can then have two separate (potentially identical) blocks of logic; one clocked directly from your varying clock; the other from your reconfigurable PLL. Depending on the clock frequency, you either use the result from one portion of logic or the other.
Cheers,
Alex
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Thanks for your suggestion. I am affraid that there is not enough FPGA memory resources to duplicate those blocks. I tried to bypass PLL output clock with dynamicaly controlled MUX, and providing direct clock to logic but no luck.
Thanks again
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