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Altera_Forum's avatar
Altera_Forum
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9 years ago

Cyclone IV PLL min input frequency

Hi, What is minimum input clock for Cyclone IV E PLL? Data sheet states that minimum Fin=5MHz, but PLL locks even to 500KHz input clock freqency. Can someone explain this to me? Thanks
Altera_Forum's avatar
Altera_Forum
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9 years ago

Hi,

Thanks for your answers. Then could someone help with the solution on how to implement interface when FPGA is clocked in range of 100kHz - 200MHz, and clock can be changed while operating?

I have implemented reconfigurable PLL to cover range 5MHz to 200MHz, but currently i dont have any ideas on what to do when FPGA is clocked below 5 MHz.