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Honored Contributor

9 years ago

CyClone IV PLL Dynamic Phase Shifting Probem

I am experimenting with dynamic phase shifting using a Cyclone IV, DE0-Nano board and Quartus 13.1. My reference input clock is 50Mhz and I have several output clocks all configured for 50Mhz as wel...

Altera_Forum

Honored Contributor

9 years ago

Check that you are using correct cntsel values see Table 5–13 on https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51005.pdf handbook. Cntsel values are different for Cyclone IV and Cyclone V, for eg. if you use cntsel=0 on Cyclone IV you will get phase shift on all outputs and on Cyclone V phase shift will be made on only c0 output.

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CyClone IV PLL Dynamic Phase Shifting Probem

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