Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Cyclone IV not stable on my PCBs, completely stumped

I've got an EP4CE10F17C8 based design that I've recently moved from an Issue 1 PCB to an Issue 2 PCB, and now it's not behaving properly. Even a very simple configuration containing just a modulo 10 LPM counter doesn't work reliably as it usually divides by 10 but often divides by 9 and sometimes by 8. The input clock is 25MHz from a crystal oscillator module. The supplies measure fine and don't show any unpleasant noise. I've kept the same decoupling arrangement on Issue 1 and Issue 2 PCBs, and the EP4CE10F17C8 configures fine either by FPP or JTAG.

Does anyone have any suggestions as to what I've overlooked?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Does anyone have any suggestions as to what I've overlooked?

    --- Quote End ---

    Clock noise (is the clock source routing the same?) (Are you using this raw or through a PLL?)

    Incorrect capacitors/ other components loaded in rev2.

    Floating reset input?

    ?

    Nial
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thanks Nial, it's looking like a clock problem. I tried putting the clock through a PLL and that seems to have fixed it. I'm still a bit mystified because the clock signal looks clean at the driver and only travels along about 30mm of track.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi Oliver,

    is the track for the clock identical in terms of corners and/or via? It seems like there is a disturbance by the clock signal reflection on the PCB... Or - even if this may sound stupid (and I have not yet checked if there is any effect on this) - the level configuration may mismatch, i.e. the Cyclone clock pin being configured as LVTTL 3.3 and your's oscillaltor being 3.0V type...

    It is definitely strange, I've never had this with the CLK signal and dedicated CLK pins of Cyclone IV - I know this for external inputs used by state machines if these are not synchronized to clk before...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    The tracking got changed because I had to move the FPGA to clear a mounting hole. I also asked my PCB guy to uses thicker tracks where possible to improve manufacturability. I didn't sweat the clock track too much because it's so short. I'll be looking at it a lot harder next spin!