Cyclone IV GX Tranceivers

A lot of transceiver interfaces are AC coupled, so then it is only the voltage swing that needs to be compatible.

If your fiber interface is being used to transmit encoded data, eg. 8/10B, then an AC coupled link to the FPGA PHY would be possible.

Take a closer look at the fiber transceiver documentation.

Cheers,

Dave

Yeah It is AC coupled, and in the past we used external tranceivers with a cyclone II, These tranceivers were 8B/10 encoded. I am pretty certain it would work. Is there are place to find the voltage levels for these standards. I have been searching and haven't really found much.

And I have seen LV-PECL to LVDS schematics, so if you know of any PCML to LV-PECL schematics that would be helpful. thanks

--- Quote Start ---

Is PCML the same standard as CML?

--- Quote End ---

I don't know. As a matter of experience though, ignore whatever 'standard' the data sheet description for a part says it uses, and look at the technical details in the datasheet.

For example, I used a PLL part from Analog devices that says it has CML outputs. CML outputs should have pull-ups to the supply rail at the transmitter ... but this particular part does not ... so it was CML 'compatible' (with the addition of external resistors), rather than CML compliant.

For AC coupled links, the things you want to find in the data sheet are the input voltage differential minimum and maximum at your receiver, and the corresponding output differential possible from your transmitter. If you find an incompatibility, then it needs to be resolved. If the transmitter amplitude is too big, then a termination/attenuation network can be used. If the transmit amplitude is too small, then you need a different part (or high-speed comparator between the transmitter and receiver).

Cheers,

Dave

Erm..

Acording to the datasheet, LVPECL and PCML are only supported as clock inputs. General clock or dedicated REFCLK for transceivers.

Transceiver I/Os should still be LVDS.

--- Quote Start ---

I don't know. As a matter of experience though, ignore whatever 'standard' the data sheet description for a part says it uses, and look at the technical details in the datasheet.

For example, I used a PLL part from Analog devices that says it has CML outputs. CML outputs should have pull-ups to the supply rail at the transmitter ... but this particular part does not ... so it was CML 'compatible' (with the addition of external resistors), rather than CML compliant.

--- Quote End ---

^^ A very good advice.

That said, PCML should be just another name for PECL.

The voltage levels are higher than LVPECL but the voltage swing should be the same (0.8 V).

LVPECL: low => 1.6V, high => 2.4V

PCML: low => 3.4V, high => 4.2V

Hi

Just to say I made a print and I am successfully driving a SFP fibre-optic module (I used a Finistar FTLF1322P1xTR). There was no circuitry needed, the voltage swing is the only consideration because the SFP module is capacitor coupled and terminated anyway.

It was a little scary because I did this when the Cyclone IV GX was a very new chip and nobody could say if it would work. But everything is working just fine.

No problem.

--- Quote Start ---

Hi

Just to say I made a print and I am successfully driving a SFP fibre-optic module (I used a Finistar FTLF1322P1xTR). There was no circuitry needed, the voltage swing is the only consideration because the SFP module is capacitor coupled and terminated anyway.

It was a little scary because I did this when the Cyclone IV GX was a very new chip and nobody could say if it would work. But everything is working just fine.

No problem.

--- Quote End ---

So I built the Board using my fiber tranceiver and a cyclone iv gx. It works half the time. Sometimes I power it up and it works and continues to work. And other times I power it up and it recieves nothing. What did you do with the reset. Did you do automatic lock or manual lock. I also noticed my rx_freqlocked bit is stuck high. did you have the same problem.