Cyclone IV GX PCIe SOPC design

Guys, thanks for your posts and I agree with you that Altera didn't do its best to provide a well structured or sufficient documentation for a rapid hands on experience.

Meanwhile the problem was solved ! The problem was the lack of a RESET signal routed into the PCIe block.

Here is the solution, maybe there are others who can benefit from it. I will describe only the mandatory connections:

INPUT connections:

-> fixedclk ( 100 Mhz clock, NOTE: it must be derived from a source other than the free running PCIe clock ( here refclk ))

-> reset_n ( reset source for the PCIe hard IP core (active low) it should be bound to high or to an external reset source )

-> pipe_mode ( connected to '0' (Virtual Pin) )

-> reconfig_clk ( connected to '0' (Virtual Pin) )

-> reconfig_togxb [3..0] ( connected to '2' (b0010) (Virtual Pins) )

-> refclk ( 100 Mhz (settings in PCIe compiler must match clock sources) )

-> rx_in0 ( RX line(s) - this design uses PCIe X1 )

-> others -> unconnected

OUTPUT connections:

-> tx_out0 ( TX line(s) - this design uses PCIe X1 )

-> others -> unconnected

On the forum some remarked that it is needed an external reconfiguration block (ALTGX_RECONFIG) , it seems that this is unnecessary and using the constant values described above for the reconfiguration block pins should be enough.

Hope this helps.