Cyclone IV GX LVDS clock input resistor termination

The GxB reference clock input have HCSL standard, not usual LVDS. That's basically the same with all Altera Gigabir receivers. They need AC coupling for LVDS.

The termination implemented in DevKit, both for PCIE originated RefClk (HCSL standard) as well as internal generated crystal clock (LVDS standard) is not according to the suggestions in the hardware manual (Fig. 1-22 respectively 1-23). I'm not using Cyclone IV GX yet and can't tell, if it can work reliabably, though. If you are designing a new board, you may want to file a support request before.

P.S.: I think it would be safe to provide the termination suggested in the hardware handbook in both cases. Rs is usually set to 0 with common PC motherboards.