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Altera_Forum's avatar
Altera_Forum
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8 years ago

Cyclone IV FPGA communicate with CPU by pcie

hello guys,

I use the cpu communicate with fpga by pcie and the cpu is the RP and FPGA is the EP.In RP i can read the EP vender ID , device ID , BAR mask and allocate pcie address for EP.but when i send data to EP, the EP cann't receive the data.What question cause this problem?

Please give me some help!

thank u very much!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi Sunny yang,

    Apologize in advance since I’m not the expert in PCIe application, so I won't be much of a help here. Are you using your own software driver in the CPU (RP) to communicate and send the data to the Cyclone IV (EP)? Or are you using the example design from AN456 to test the PCIe performance in Cyclone IV device?

    https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an456.pdf

    I that suggest that you re-post this question in the IP Discussion forum in order to get the right help among the PCIe and IP communities or users. Refer to the following link:

    https://www.alteraforum.com/forum/forumdisplay.php?f=9

    Regards,

    nyusof

    (This message was posted on behalf of Intel Corporation)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi,

    Have you checked this PCIe IP via Simulations to see if the EP is getting configured correctly. If read/writes work in the simulations , then the IP is not at fault. On the board side, you say that you can get the DeviceID, BAR and Config space of the PCIe EP. Have you checked if link training is happening correctly. I believe that there's a signal from the EP that denotes link training is done. If you check this signal via Probe or route it to a GPIO/LED via the FPGA you will get a visual indication that the EP is configured correctly.

    The CPU RP should attempt to read the EP registers and status and be able to configure the EP in the FPGA. This happens via a set of BAR reads and writes. Make sure that the PCIe configuration is done before you attempt to do any data reads/writes. If this is not done, the EP will not know what its supposed to do with the data that is sent to it. Most likely, you will set up another device/IP in the downstream ports of the EP to be configured either as Memory-mapped IO or IO mapped, so that the EP will pass the data from RP CPU to the targeted device downstream.