Honored Contributor
Honored ContributorThe setting you refer to applies to ALL I/O that is not explicitly identified in your design. So, it must suit both those signals you've connected to GND and the others.
The first thing to mention is that all the pins you've identified are dual purpose and the primary function of all (except the clocks) is general purpose I/O. So, unless you require the specific functions available - DEV_CLRn, CLKUSR, etc. - and you specify this in your Quartus project, then they will simply remain unused I/O. The clock signals will remain unused inputs. By tying the signals you mention to ground you have already designed a board on which you cannot use the dedicated functions the pins offer. For example: if, in your project, you specify that you want to use DEV_CLRn and it's tied to GND on the board, your FPGA will do nothing, ever. This is perfectly OK :) - if you don't require this function and you're not intending to use this pin as I/O then you've done the right thing. Based on the information you've offered I recommend you select option a) 'inputs tri-stated', unless you really have a board which has been specifically designed with the intention of selecting e) 'outputs driving ground'. This option offers various noise benefits but is typically only used once a design has been thoroughly proven through testing and the PCB re-spun accordingly. Don't use option d) based on the fact you've grounded some of the I/O. Options c) and d) offer you nothing as the majority of your unused I/O is unconnected. Regards, Alex
