Cyclone III stuck at POR?

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The Cyclone III handbook recommends 10k pull-ups for both TDI and TDO, but I think it's not very critical. In my circuit I have 1k pull-ups at TDI and TMS and a 1k pull-down at TCK, they're placed on another sheet of the schematic.

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I agree that the pull-up resistor values aren't critical. Using a higher pull-down resistance for TCK has cshown a problem in some cases, where TCK picked up interferent signals, causing random faults in operation.

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I've heard that the TCK signal is sensitive to trace length and noise - can anyone confirm this? I'm told a 1 to 10pF cap to gnd can fix some issues...

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I recently reported the case of a Cyclone design, where a capacitor was needed to achieve reliable TCK operation. The FPGA was still recognized by the programmer, but some JTAG action failed, e.g. indirect JTAG programming and SignalTap II operation. If I remember right, some problems with Cyclone III Dev Kits could be also fixed this way. In my understanding, it's a special problem of TCK signal integrity, involving the USB Blaster driver impedance and on-board wiring. I have much more Cyclone I - III designs, where JTAG operations never brought up any issues.