Honored Contributor
Honored ContributorHello FvM,
--- Quote Start --- You didn't explicitely tell, but I assume that the device also isn't recognized at the JTAG interface? --- Quote End --- Right, the device doesn't respond to JTAG commands. This and the LOW nSTATUS pin are the reasons why I assume that the device is stuck in POR. --- Quote Start --- I assume, that some optional resistors at the configuration interface aren't populated (e.g. nCONFIG pull-down), otherwise, the above reported measurements won't be plausible. --- Quote End --- The parts marked with "NB" are not populated to the board. But the nCONFIG pull-down is populated, the pin is driven HIGH from outside by a PCIe to local bus bridge. It will pull nCONFIG high as soon it has finished it's initializing sequence that is longer than the FPGA's POR. So, while the FPGA is in POR, nCONFIG will be LOW. Some 100ms later it will be pulled HIGH, and that should start configuration. I did this the same way with a previous design with a Cyclone I. Do you think this should work with the Cyclone II devide, too? --- Quote Start --- A small detail, that I don't undertand is L3 at the EPCS supply pins without any bypass capacitors. --- Quote End --- Yes, this is how it's designed. L3 is a small ferrite that should stop EMI. I know it's unusual without a decoupling resistor at the chip's pin, but it was a recommendation from a EMI siminar and it worked well in former designs. Regards, Jürgen
