Cyclone III queries.

Brad is right, that you have to connect the pins to some logic for a final verification of a pinout. To allow parallelisation of work, it's usually O.K. to use the Pin Planner result to start schematic entry and possibly layout, but at least connect the said dummy logic before producing a prototype. It's better of course, if you are already able to verify the timing with a full design. You surely can imagine, that it's a matter of experience to foresee typical trapdoors in pin assignment.

If you have LVDS and LVTTL I/O, you need 2.5V and 3.3V banks, very simple. As said, you can place LVTTL inputs in a 2.5V bank but no outputs that require full Voh level.

I also agree with Brad, that some of your question can be answered more easily by trial, although Pin Planner is a powerful tool. Some details are possibly clearer in the device pinout files. Generally DQ/DQS and DIFFIO have no particular relation, they are simple optional pin functions, sometimes alternative at the same pin. With Cyclone families, all DIFFIO pairs can be used as input, output properties are different in different banks, e.g. some needing resistor networks.

The amount of DIFFIO pairs for different devices and packages is listed in the device handbook, also all other resources that are important in part identification. As an advantage, the Pin Planner also considers distance rules, that have to be kept with differential and voltage referenced I/O standards and may reduce the number of available pins in a design.