Cyclone III queries.

Rather than trust my understanding of what the device handbook says about some things, I prefer to create test cases in Quartus to see for sure how it works.

You can have a 3.3-V LVTTL input in an I/O bank containing LVDS. LVDS uses a 2.5V VCCIO, and that VCCIO is acceptable for 3.3V inputs. In Cyclone III you will probably get a warning with the help page for the warning referring you to Application Note 447.

The I/O count will use 2 of the available I/Os for each of the differential pairs. A single LVDS signal is a differential pair using 2 I/Os. If you think you might use almost all the available I/Os, be careful about something else affecting how these are counted. I forget how special pins are included in the stated quantities of available and used I/Os. I had a situation in some device where I had to look at this very closely in Quartus to see for sure how many I/Os were actually available for regular signals.

Before you commit to a pin-out for board layout, have a Quartus project that contains at least your I/Os, PLLs, and configuration scheme. Use dummy logic as necessary to keep the clocks from synthesizing away. If you are using IP with special I/O restrictions like a DDR memory interface, then include that IP in the project used to do the pin-out check. When using a combination of I/O standards where certain pins must be kept a certain distance from other pins, include enough dummy logic to make the data pins toggle or use "Toggle Rate" assignments. Run at least I/O Assignment Analysis, preferably the complete Fitter.