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Honored Contributor
Honored ContributorCyclone III queries.
Hi all, I just have a few queries regarding Cyclone III that I was hoping you guys could help me with. At the moment I am working on choosing an suitable FPGA for a new project. It´s the first t...
Altera_ForumHonored Contributor
Honored Contributor1. Very simply, you can mix I/O standards in a bank, but you can't mix I/O supply voltages. LVDS must be supplied with VCCIO of 2.5V. You also can place 3.3V inputs in this bank, but no 3.3V outputs (cause Voh doesn't meet the specification). The device handbook tells in detail how and why.
2. 347 user I/O mean pins. A LVDS in- or output need two (adjacent) pins. It's generally advisable to perform pin assignment in the Pin Planner tool, to be aware of any incompatibilties in time. 3. Due to temperature dependant timing parameters, the fastest speed grade most likely isn't available in industrial grade. I think, you're right regarding limited demand and slowest grade.
