When you look at the latest CIII specs, you can see that typical core power is much lower for C3 compared to C2 (for example, typically 3mA for EP3C16 vs 37 mA for EP2C15). Very nice.
**BUT ** :( , what a pity to see how much C3 PLL consumes compared to core power ( overall PLL consumption is about 38mW typically for an EP3C16, versus 4.8 mW core power !!).
I really wonder why C3 uses 2.5V for powering analog PLL, instead of 1.2V as the C2 does?
IMO, this is neither power efficient nor cost efficient (you have to add an 2.5V LDO exclusively for PLL power)
It would be wonderfull to have a next C3 generation, or a derivative, reverting to a single 1.2V power rail for PLL voltages. That would help C3 devices to compete with some other "low power" flash based devices. An other annoying thing is that you have to power these ungry PLLs , even if you don't use any of them. Hey Mr Altera, not all design uses PLL in embedded world :D
A very power conscious user...:rolleyes: