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Altera_Forum's avatar
Altera_Forum
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14 years ago

Cyclone III output termination for 3.3V IO standards

Hello,

It appears that Cyclone III family has extremely limited output control capabilities for 3.3V IO standards. There is no ODT, no slew rate control and only 3 current strength settings are available: 1 for LVCMOS_33 and 2 for LVTTL_33. It appears that the only option to assure adequate signal integrity is to place external serial resistors for all outputs - something usually not required in FPGAs.

Is this a trend Altera is promoting to phase out 3.3V IO standards, or a specific shortcoming of Cyclone III family?

Thank you.

michagal

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The restriction for 3.3V IO standards applies to higher output currents. In the range, where external series resistors comes into play, it doesn't provide less adjustment granularity as previous types, e.g. Cyclone or Cyclone II.

    To match higher trace impedances, e.g. 70 ohm, you'll need series resistors as before.

    Obviously Altera tries to reduce the permitted current level for 3.3V IO standards, which can be seen as a concession to 65 nm technology. Interestingly, newest Cyclone V family has re-enabled a 16 mA current strength for 3.3V LVTTL.

    With Cyclone III, Altera has started to emphasize the problem of signal overshoots conflicting with maximum ratings. You'll find "watch your step"-like warnings allover the documents. Taking a closer look at overshoots occuring in some designs, it's understandable somehow.