Honored ContributorI'm designing with LVDS for the first time and want to make sure I don't overlook something simple. It looks like 2.5V VCCIO is mandatory. The EP3C5 pinout document tells me which pins can be LVDS. I specify the pins as LVDS in the pin planner. Can I mix single ended and LVDS signals in the same I/O bank?
Honored ContributorThe best way is to assign all your pins and their io standards then run analysis tool to check your early pin planning. You don't need logic but you must define pin direction and may insert dummy logic e.g. inputs driving outputs. You better insert all your PLLs and any IP cores needed for io(DDR, tranceivers...).
devices differ and some pins support input lvds but not output or the reverse. some plls favour specific clock pins. some diff pins support specific types of voltages...Honored ContributorYou should consider the fact, that the Cyclone III I/O rules require a distance between single ended and differential (LVDS) pins.
Honored ContributorGreat, thank you both.
Honored ContributorHonored ContributorQuartus doesn't require it for differential clock outputs.
Honored Contributor
