Forum Discussion
Honored ContributorCyclone III LVDS
I'm designing with LVDS for the first time and want to make sure I don't overlook something simple. It looks like 2.5V VCCIO is mandatory. The EP3C5 pinout document tells me which pins can be LVDS. I specify the pins as LVDS in the pin planner. Can I mix single ended and LVDS signals in the same I/O bank?
6 Replies
Altera_Forum--- Quote Start --- Quartus doesn't require it for differential clock outputs. --- Quote End --- Is there any description about the disitance here?Maybe a few pads? What if the differential pin and TTL pin are in different bank,but very near?- Altera_Forum
Quartus doesn't require it for differential clock outputs.
- Altera_Forum--- Quote Start --- You should consider the fact, that the Cyclone III I/O rules require a distance between single ended and differential (LVDS) pins. --- Quote End --- How about differential clock output and differential data input ?Is there also need some distance?
- Altera_Forum
Great, thank you both.
- Altera_Forum
You should consider the fact, that the Cyclone III I/O rules require a distance between single ended and differential (LVDS) pins.
- Altera_Forum
The best way is to assign all your pins and their io standards then run analysis tool to check your early pin planning. You don't need logic but you must define pin direction and may insert dummy logic e.g. inputs driving outputs. You better insert all your PLLs and any IP cores needed for io(DDR, tranceivers...).
devices differ and some pins support input lvds but not output or the reverse. some plls favour specific clock pins. some diff pins support specific types of voltages...
