You should probably understand how TimeQuest times latches, and make sure that you are meeting timing on your circuit. By default, TimeQuest times latches as falling edge registers and checks setup and hold to the falling edge of the latch signal. You can change this behavior to have the latches timed as combinatorial logic (pass-through mode, which I think is what you want). In this mode, it will check the timing from the previous register t the following register through the latch. In order to do this, you much generate the timing netlist in TimeQuest differently with the command 'create_timing_netlist -no_latch' (by the way, this option is NOT in the GUI so you will have to type it at the console prompt, or do it by Tcl script).