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My current goal is to figure out the root cause of the problem and then develop a solution. Would it be safe to say that it is caused by a glitch? Would you recommend reworking the HDL in such a way that a latch is not generated?
Thanks!
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I wouldn't waste too much time trying to work out what's causing the problem, just accept it's something to do with how the latch is imlpemented.
Best Solution. If you have a fast clock sample the input you're trying to latch, when you see it go high drive your output high, reset low with the reset input.
Second Best Solution. Use the latch input as a clock to a register with the reset as the asynch reset, in VHDL...
process(input, reset)
begin
if(reset = '1') then
latch_out <= '0';
elsif(rising_edge(input)) then
latch_out <= '1';
end if;
end process;
Nial
Honored Contributor
