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Altera_Forum
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15 years ago

Cyclone III EPC120F484C8 LVDS speed

Hi, I'm planning to use a Cyclone III EPC120F484C8 to read the data from an ASIC. The ASIC has 50 parallel output bits (25 LVDS pairs read using clock A, and 25 more using clock B) at a continu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I've been reading the documentation, but perhaps you can point me to the right chapter/section. I have a small daughter card with a Cyclone III EPC120F484C8 and enough LVDS I/Os. As I said, the FPGA is only collecting the data from 50 LVDS pairs in parallel (no serialization). Every clock cycle i need to collect the data on the 50 LVDS pairs. The clock runs at 200MHz. I'm just trying to make sure the FPGA can do the job.