Honored Contributor
Honored ContributorI let it run while I was on vacation for a week and when I got back it was still running. It gets stuck at the Fitter(place and route) step at 80% completion. I don't get any errors if that is what you mean. I do get a message that says it has been running for x hours. It gets to the same place Fitter(place and route) 80% if I let it run overnight. I tried running it with the compiler options turned down, and it did finish in about 20 min in the lowest setting, but it didn't meet timing. If I run it in the med setting where it will make it meet timing and perform no more optimizations I sill get the long compile time.
I had added several Ethernet cores (7) to try and make the design bigger. I think this could be causing my problem because when I did the failed timing run, the part that failed was the 125 MHz clk. In my real design I intend to only use 2 Ethernet cores. I am trying to figure out how much utilization you can practically get out of the device so I can plan my required margins. This is the first time I am using an Altera device and so I am trying to establish a good rule of thumb for utilization throughout the design process. Do you know of an example design that is quite large?
