Cyclone III configuration

Such inofficial statements may be understandable by the amount of service requests and customer complains related to JTAG configuration. I can't see, that the Terrasic variant is generally superior to Altera, I could also report an example where only Altera is working correctly and a customer, who uses a ESD protection circuit for JTAG interface in all designs never had any JTAG problems, with either Altera or Terrasic Blaster .

Apart from the special problem of getting overshoots that may damage the FPGA, which can be effectively eliminated by protection circuits, most JTAG problems are centered around TCK signal quality while setup and hold times and levels of the other signals are far from being critical normally. So any means, that achieves a clear, monotic signal at the FPGA TCK pin is a solution for the issue to my opinion.