Honored Contributor
Honored ContributorNo, it's the 2.5V I don't use anywhere - as a signalling level. I do use it for the VCCA and VCCD_PLLn pins. I need every pin I can get and will definitely use the IO banks 1 and 6.
_________ I had the older version of the databook which had a mistake which was corrected in the newer version. The old version had us connecting the pull-up of the nSTATUS and CONF_DONE to the "same supply voltage as the USB-Blaster" the new version corrects this to "the VCCIO supply of the bank in which the pin resides". This still leaves me with a 2.5V signalling environment on bank 1. As I said before I don't have any 2.5V signals on my board. (To Clancy: What do you mean by "be really careful" with the USB Blaster? It seems to me that either it blows up the FPGA's inputs or it doesn't, I don't see how I can be "really careful".) Is there some way to add protection diodes to the JTAG signals and then use 3.3V for both the JTAG and Bank 1? ... or perhaps a buffer would be safer?
