Cyclone III configuration

Funny post :)

The real story is that you CAN connect the JTAG pins via pull-up to 3.3V, but it is not recommended because the overshoot caused by the download cable may damage your FPGA. So if you are going to be really careful, go ahead and use 3.3V for JTAG.

If you decide to use the recommended 2.5V for JTAG though, you can still use 3.3V or whatever else VCCIO you need for any bank, including 1 and 6. Voltage level translators (especially the step-down ones) are really simple, use a resistor divider to get your 2.5V level CONF_DONE and whatnot :)

Read the ciii design guidelines (http://www.altera.com/literature/an/an466.pdf), page 22 onwards, for info about JTAG connections.

Edit: by the way, where did you get page 10-73 on the Cyclone III Handbook, my copy I downloaded just now stops at page 10-70 before jumping to 11-