Hi I'm confuse with Cyclone fpga family and configuration schemes. In school we have an Altera board with a Cyclone II fpga, I know that the board use an EPC2 configuration device and we use the usb blaster download cable to download configuration data to the FPGA. Now if I have a board with a Cyclone III fpga and I want to use the usb blaster, what should I use? Active serial? Pasive serial? I don't understand differences between configuration devices, enhaced configuration devices or serial configuration devices. Any help will be great, thanks. :)

The USB blaster can program the FPGA itself in whatever configuration you use, as JTAG mode overtakes all the other modes. Themode to use depends on the configuration device you want to use and how it is connected. The easiest way with the Cyclone III is an enhanced configuration device (EPCS) in an active serial mode, as described page 9-13 of this document (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf). With the Cyclone III you don't need to connect the USB blaster to the flash memory, you can program it by going through the FPGA and use a Serial Flash Loader image.

Thanks, the only differences between EPCS devices are the memory size? How should I choose the right one according to the FPGA? The Cyclone III EP3C40 for example, in the document there is a table (9-3, in page 7) has something to do? or is there something else I have to check?

Yes, this table gives how many bits you need to hold one FPGA configuration and can be used to select the EPCS chips you can use. There is also a datasheet for the EPCS components on the Altera web site. The main difference between two chips is the memory size, but there can also be different physical sizes. Some EPCS chips are SO-8, and other ones are SO-16. You may need more space than that on your flash device. For example if you plan to use two designs (one as a bootloader and another one as the application) then you need to double that size. If you want to store a software application or some extra data then you need space for that too.

Oh ok, I think I understand a little more, where else could I read about configuration schemes? besides data sheets :)

--- Quote Start --- Oh ok, I think I understand a little more, where else could I read about configuration schemes? besides data sheets :) --- Quote End --- Sorry, you really do have to read the data sheets ... after a while (and a little experience) they do start to make sense :) Here's a description of how to design your own: http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf) For comparison, read the Altera PFL guide http://www.altera.com/literature/ug/ug_pfl.pdf Then look at the different options in the handbooks for the different FPGAs. The explanations are all very similar. Cheers, Dave

Cyclone III configuration scheme | Altera Community

18 Replies

Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

Then, the second scheme (JTAG) is like figure 9-30 ? http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf

--- Quote End ---

Yes, this scheme supports configuration from EPCS, and reprogramming of the EPCS device via JTAG. However, you must take care and read the footnotes - (2) indicates that you need to refer to Table 9–7 on page 9–11 for the MSEL options that can be used with AS mode.

--- Quote Start ---

How should I connect MSEL pins? according to table 9-7 all pins to GND is ok?
--- Quote End ---

Grounding all MSEL pins is not a valid Active Serial (AS) mode. Re-read the table, and you'll see several options for AS mode. The mode to select depends on the rest of your board design.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Thank you both for the MSEL pins explanation

I have one more question about .sof and .pof files, I remember we used .pof file at school, I know .pof is Programmer Object File and .sof SRAM Objet File but, files are indifferent of the configuration scheme used? what is the relationship between files and configuration schemes?
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

I have one more question about .sof and .pof files, I remember we used .pof file at school, I know .pof is Programmer Object File and .sof SRAM Objet File but, files are indifferent of the configuration scheme used? what is the relationship between files and configuration schemes?
--- Quote End ---

.sof is the file you configure the FPGA with via JTAG.

That same file can be converted to other formats for an external programmer, eg., .rbf format, Jam STAPL format, etc.

My experience with .pof files is that they are the configuration files used when programming EPC2 configuration EEPROMs, so they are basically .sof files reformated to whatever is required by the EPC2 device.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
ohh ok I understand now, thanks for all your answers they have been very helpful, I'm going to work in my design
Altera_Forum
Honored Contributor
14 years ago
Hi again,

I tested my design and its working!!! :o

I've only programmed simple things to check I/Os in my board, but it is doing well.
I want to thank you, all your answers really helped me a lot.

But I have one more question, when programming, it really takes a while erasing the device (I use an EPCS64), then quickly program and verify (almost 2minutes in total), is this normal?
The first time I programmed the FPGA almost had an attack due to expected, in college I was used to quickly program (with a EPC2).
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

I tested my design and its working!!! :o

--- Quote End ---
Excellent!

--- Quote Start ---

But I have one more question, when programming, it really takes a while erasing the device (I use an EPCS64), then quickly program and verify (almost 2minutes in total), is this normal?
The first time I programmed the FPGA almost had an attack due to expected, in college I was used to quickly program (with a EPC2).
--- Quote End ---
It depends on what tool you are using; some use a chip erase command to erase the flash, while others use sector erase on just the sectors that need to be reprogrammed.

So how long to these take? Well, lets look at a 128Mbit SPI flash data sheet:

http://www.micron.com/~/media/documents/products/data%20sheet/nor%20flash/5975m25p128.pdf (http://www.micron.com/%7e/media/documents/products/data%20sheet/nor%20flash/5975m25p128.pdf)

Bulk erase time = 130 to 250s
Sector erase time = 1.6 to 3s

Read the documentation for the various tools, or signal tap the EPCS interface and see what SPI flash command (sector or bulk erase) is being issued.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Oh ok, thank you for the info.

I'll keep reading and practising with my board, hopefully someday I'll also answer some questions in the forum :)
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Oh ok, thank you for the info.

--- Quote End ---

You're welcome.

--- Quote Start ---

I'll keep reading and practising with my board, hopefully someday I'll also answer some questions in the forum :)
--- Quote End ---

Please do!

Cheers,
Dave

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Cyclone III configuration scheme

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