Cyclone III AS Configuration

Thanks for the suggestions. The schematic is identical to the design referenced in Figure 10-29 in the Cylcone III handbook (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51010.pdf) on page 10-58. I checked to see if the FPGA was issuing the command to get the device ID from the EPCS16. To check to see if the connections were ok I assigned each of the pins (DCLK, ASDO, and DATA) a clock output from the FPGA and measured it on the JTAG header pins. The clocks looked ok except for on the ASDO pin where there was a lot of ringing.

(http://www.altera.com/literature/hb/cyc3/cyc3_ciii51010.pdf)

This figure shows DCLK in yellow, ASDO in green, and nCSO (the EPCS16 chip enable) in purple. It looks like the ASDO pin is trying to issue a command but it seems like something is wrong with the trace. Does this seems like an accurate diagnosis? Are there any software settings in Quartus that have to be set for AS to work? Unfortunately, I only have 1 board to work with until tomorrow so I can't see if the problem is reproducible.

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