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Honored Contributor
Honored ContributorCyclone III AS configuration bizarreness
I am using a cyclone III (EP3C25F324C8N) with an EPCS16 configuration device. I am programming the configuration device through the FPGA with the serial flash loader. The problem is that the Cyc...
Altera_ForumHonored Contributor
Honored ContributorYou possibly need an active probe to see the CLK signal undistorbed, The final cause for configuration problems related to JTAG signal quaility is often a non-monotic, ringing CLK edge, which is seen as double clock edge by the JTAG logic. A small capacitive load like the 10 or 12 pF of a standard passive 10:1 oscilloscope probe can be already sufficient to fix the problem.
Placing a small capacitor, e.g. 15 or 22 pF between TCK and ground near the FPGA would be my first try to solve issue.
