In our FPGA work we tend to use software(C for nios) when dealing with slow and/or algorithmically complex work. Any fast data processing is left to hardware(firmware).
The unit comms, user interface, any external configurations and other once only or so slow things are certainly left to software colleague if he/she is kind enough, if not you can do whatever you can in firmware until you are exhausted then seek the help of your manager to throw some work on the software team.
It is always useful to remember that you are not alone with your HDL fun and that you got software support for any difficult nasty tasks provided it is a match to software speed even if this task is a corner somewhere in the middle of your design.