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Altera_Forum
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16 years ago

Cyclone III and 400 Msps DAC

I want to drive a 400 Msps DAC (DAC5675A) with EP3C16Q240C8. The FPGA 's PLL cannot create a 400 MHz clock for the DAC due to hardware constraints, although it can produce 400Mps LVDS DATA thanks to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Yes, this should work. You can output a testpattern, determine the clock phase limits, that still achieve correct DAC output and set the phase shift to the mean value.