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Altera_Forum
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16 years ago

Cyclone III and 400 Msps DAC

I want to drive a 400 Msps DAC (DAC5675A) with EP3C16Q240C8. The FPGA 's PLL cannot create a 400 MHz clock for the DAC due to hardware constraints, although it can produce 400Mps LVDS DATA thanks to ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I'm planning to use a separate clock generation chip in order to create the 400 MHz clock required by the DAC. The tx_outclock provided by the FPGA PLL should be the Reference CLK for this purpose. I also think I' ll have to use the "PLL LOCK" output pin of the external chip as a latch enable for the LVDS Data Transmission. The question is, how am I going to synchronize the LVDS Data with the Clock, so as the DAC will sample them properly? Should I try the “Specify phase alignment of ‘tx_outclock’ with respect to ‘tx_out’” option of the ALTLVDS Megafunction? . Any ideas are welcome,

thank you in advance!