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Honored Contributor
Honored ContributorCyclone III and 400 Msps DAC
I want to drive a 400 Msps DAC (DAC5675A) with EP3C16Q240C8. The FPGA 's PLL cannot create a 400 MHz clock for the DAC due to hardware constraints, although it can produce 400Mps LVDS DATA thanks to ...
Altera_ForumHonored Contributor
Honored ContributorI didn't get the meaning of "External PLL" in your post, because I'm using mostly "external" PLLs resepectively custom LVDS transmitters with Cyclone family. Yes, the LVDS function needs 2 different clocks, so the PLL has 3 clock outputs available for other purposes. Even a combination of two cascaded PLL's can work, but it would involve higher clock uncertainty.
Just for fun, you can evaluate the actual maximum toggle rate of your FPGA by faking a EP3C16xxxC6 chip.
