Cyclone III and 400 Msps DAC

FVM, thanks for your really quick reply.

Actually i m thinking of using the ALTLVDS Megafunction along with an "external" PLL (ALTPLL Megafunction) to clock the data. That PLL can provide slow and fast clocks for the Tx and also the reference clk for the distribution chip so that LVDS Data and CLK can be synchronized for the DAC. The thing is, that theres is also an SRAM chip that feeds the slow data to the ALTLVDS Tx, and this chip has to be clocked too, so maybe that Megafuncion PLL can also take care of that (200MHz) CLK needed there. Is synchronization of all this clocks possible? Changing the FPGA is not really possible for many reasons. Thanks a lot

P.S: While the PLL can create output clocks of at most 300 MHz, when editing the output clock frequency value of the Megafunction, the "Able to implement the requested PLL" Message appears even for values of 600 or 900 MHz. Of course, during simulation Quartus warns that these frequencies cannot be implemented. Is it some kind of bug?