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Altera_Forum
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16 years ago

Cyclone III and 400 Msps DAC

I want to drive a 400 Msps DAC (DAC5675A) with EP3C16Q240C8. The FPGA 's PLL cannot create a 400 MHz clock for the DAC due to hardware constraints, although it can produce 400Mps LVDS DATA thanks to ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Yes, the C8 output toggle rate is limited to 320 MHz. So you need an external clock doubler circuit. Using a faster (C6 + BGA package) CIII version may be the more simple solution. The 200 MHz LVDS clock can be still generated from an internal PLL in my opinion. A fine tuning of LVDS versus external 200 MHz clock phase is most likely necessary, but basically a simple action.