Honored Contributor
Honored ContributorHi Anakha,
Thank you for your reply. i agree with you that the failure should move with the several synthesis runs I did, but the failure is always on the same memory block, so I also guess it has nothing to do with which memory block is used and I also asume for now that there is no timing issue, because the reports do not report an timing error. But, until today I still have the error and made some extra logs with signal tap. three instantiations, three identical timing diagrams, but one memory block fails ... I keep on searching for this interesting bevaiour. Bye, Bert
