Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Cyclone III-120: M9K read, write failure

Hi, In our design I have a custom memory controller connected to the Avalon MM bus, with one Avalon MM interface, and at the other side of the controller I have four instantiations of 512x32b memo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi Bert.

I've uses the Cyclone III's since their release, (Mostly the 3C25, 3C40, 3C55, and 3C80)

I have never seen the issue you have described. You stated you can see the Writes happen and the Read's fail, Are you tapping right at the port of the ram instance? My thought is either a clock, write enable or read enable is not connected properly. You would think these issue would show up in simulation however.

If it was a bad M9k, you would think the problem would move around from synthesis run to synthesis run.

If you post the code snippet, I'm sure someone can be of more help.