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Also, I'm not using dedicated clock output for the clock (oversight in the board layout). How can i determine the max skew for a PLL clock output on a regular device I/O pin?
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It is generally better to drive a source synchronous output clock on a regular I/O pin using the same output-register setup as the output data than it is to drive the clock with a dedicated PLL output. Typically the clock is driven with DDIO registers in the I/O cell (can be as simple as tying one register input to a hard-wired high and the other to a hard-wired low unless you want to be able to stop the clock). For the least clock-to-data skew, the data is also driven by DDIO registers even if the data is single data rate (in that case connect the internal data signal to the inputs of both DDIO registers).
For HardCopy II, the clock output should be driven by a dedicated PLL output. For a Stratix II design that might go to HardCopy II, the clock can be driven by a dedicated PLL output that has DDIO registers available so that the FPGA drives the clock with the registers and the HardCopy device drives the clock with the PLL output directly with the same board layout for both devices.
Jitter will probably be less using the dedicated PLL output. I think I've seen a device handbook where the jitter was specified separately for a dedicated clock output and a regular I/O, and it was higher for the regular I/O. This is probably the case for Cyclone II.
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