Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Cyclone II PLL Skew?

Hello, How can i determine the max clock skew on an output pin on my Cyclone II? I would like to know if clock skew could be significant enough to warrant being part of the SDC constraints for ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

As long as you have properly constrained the pin to be the clock for the source-synchronous interface, Quartus will take the skew into account. There is a free video tutorial on Altera's website about constraining source-synchronous interfaces. You should follow the guidelines indicated there.

Jake