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Honored Contributor
Honored ContributorCyclone II PLL ESD Sensitivity
Hi all! I have a problem with a Cyclone II design. I have taken a lot of measures against ESD and power supplies remains stable when discharging to the board connectors. I am howev...
Altera_ForumHonored Contributor
Honored ContributorYou should use safe coding for the state machines, otherwise a clock timing violation may cause a state machine to get trapped forever in an illegal state. If your design doesn't depend on the phase relation of different PLL output clocks, a PLL reset isn't absolutely required, I think.
