Forum Discussion
Altera_Forum
Honored Contributor
18 years agoLarsen has a point here.
Take a look at the "check(dmx_in)". What is the source of the dmx_in signal? Is it clocked somewhere before entering the state machine? Or is it an external signal coming directly from a pin or from another clock domain? Sounds like a timing or meta-stability problem when the behaviour is erratic.