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Altera_Forum
Honored Contributor
18 years agoWithout having looked into any details of your design I would ask:
are all inputs to you statemachine syncronized before entering? I.e. they should pass at least one DFF clocked at the same clock as the SM. If not, you may end up having metastable state FF's, which will manifest exactly what you see: Erratic performance now and then. Second point is: Check for warnings in timing analyser.